Quantum Error Correction:
Quantum Low-Density Parity-Check Codes Workshop

Photonics offers a modular, highly networkable hardware platform with room-temperature integration, unlocking critical flexibility in the design and implementation of advanced quantum error-correcting codes. In this talk, I will detail Xanadu’s approach to photonic fault-tolerant quantum computing using concatenated GKP-qLDPC codes. I will first provide an overview of the architecture's foundational components and discuss our full-architecture prototype, Aurora. I will then dive into the core challenges of correlated noise and executing reliable logical operations. To address these, I will present our specialized decoding methodology tailored for correlated noise, alongside our approach for executing fault-tolerant quantum computation via Pauli product measurements (PPMs) driven by homological measurements. Finally, I will share numerical simulation results that validate these methods and highlight their advantages.

LDPC-based architectures have the potential to significantly reduce the resources required to run useful algorithms on fault-tolerant quantum computers. On the theory side, much of this progress happens at a hardware-agnostic level, through work that pushes down overheads independently of any particular device. On the hardware side, there are now a diverse range of LDPC-compatible platforms capable of going beyond nearest-neighbour fixed connectivity and with plans to scale to the size required for useful quantum computing within the next few years. As these two lines of progress converge, an important priority becomes hardening and deploying these efficient fault-tolerant architectures for real devices. This talk offers a snapshot of that work at Iceberg Quantum, focusing on how architectures like Pinnacle can be realised across today's rapidly advancing hardware platforms and integrated with the surrounding software stack.

Recent years have produced an increasingly rich landscape of quantum low-density parity-check (QLDPC) codes with attractive code parameters, thresholds, and asymptotic scaling properties. Yet a QLDPC code is only the starting point for a fault-tolerant computing architecture. Turning a code into a practical computing system requires solving a series of interconnected problems that are often far more challenging than the code construction itself: implementing logical gates, compiling algorithms into native operations, designing decoders, minimizing latency, constructing syndrome-extraction schedules, modeling circuit-level noise, and ultimately determining the true space-time cost of computation. This workshop explores the hidden work required to transform a promising QLDPC code into a complete fault-tolerant computing stack. Using the SHYPS (Subsystem Hypergraph Product Simplex) codes as a case study, we follow the path from code construction through logical gate design, efficient Clifford compilation, low-latency sliding-window decoding, detector construction for logical circuits, and deep circuit-level simulations of fault-tolerant computation. Rather than focusing on any single advance, the workshop examines how each layer of the stack constrains and informs the others, and why progress at one layer is often insufficient without corresponding advances elsewhere. Emphasis will be placed on the practical challenges that are rarely captured by code parameters alone: decoder latency, logical clock-cycle design, syndrome-processing assumptions, compilation overheads, and the interaction between logical operations and error correction. We will discuss how seemingly small implementation choices can have significant consequences for overall computational performance and resource requirements. The goal of the workshop is to provide a framework for evaluating QLDPC architectures end-to-end. Attendees will gain insight into the questions that must be answered before a code can support useful fault-tolerant computation and why demonstrating a complete computational workflow is increasingly as important as the underlying code construction itself.

Trapped-ion devices benefit from two significant advantages compared to other physical modalities: very low-noise physical gates and ease of transport. I will describe how we leverage these advantages to design a fault-tolerant architecture built on top of novel high-rate quantum low-density parity-check (qLDPC) codes. Low-loss ion transport allows syndrome circuits of qLDPC codes to be implemented with only a small number of transport steps, instead of difficult-to-implement long-range physical gates. Performant physical gates in turn allow us to prepare and verify high-quality cat-states, which are transported between blocks to realize logic via Pauli measurements. Finally, I will also describe efficient magic factories built on novel bicycle codes that admit strongly transversal Hadamard gates, that distills H-states within very small space-time footprints.

Quantum computers offer a new paradigm for scientific discovery, but their practical realization is fundamentally limited by decoherence. Quantum error correction (QEC) provides a route to overcome this challenge by encoding protected logical qubits into many redundant physical qubits. However, efficiently encoding, manipulating, and scaling logical qubits in hardware to realize useful computation remains a central open problem. In this talk, I will describe experimental and theoretical advances that substantially narrow the gap between neutral-atom hardware and utility-scale computation. First, I will present demonstrations of the key building blocks of universal, fault-tolerant quantum processing with reconfigurable neutral-atom arrays, including logical performance roughly a factor of two below threshold. I will then discuss theoretical results that substantially reduce the overhead of fault-tolerant computation. By leveraging high-rate quantum error-correcting codes, efficient logical instruction sets, and optimized circuit design, we show that Shor's algorithm can be executed at cryptographically relevant scales with as few as 10,000 reconfigurable atomic qubits. Adding physical qubits improves runtime by enabling greater parallelism: under plausible assumptions, discrete logarithms on the P-256 elliptic curve could be computed in a few days with 26,000 physical qubits, while factoring RSA-2048 integers would take one to two orders of magnitude longer. Although substantial engineering challenges remain, this analysis indicates that an appropriately designed neutral-atom architecture could support utility-scale quantum computation. More broadly, these results highlight the promise of neutral atoms for fault-tolerant quantum computing, with wide-ranging scientific and technological applications.

Quantum LDPC codes offer a route to lower-overhead fault tolerance, but their practical value depends on co-design across code construction, logical operations, syndrome extraction, and low-latency decoding. This talk presents recent QEC research at NVIDIA, from theoretical advances relevant to code construction and fault-tolerant operations to GPU- and AI-accelerated approaches for evaluating and decoding practical qLDPC architectures. I will also discuss NVIDIA’s decoding software stack, including CUDA-Q QEC implementations of belief propagation, BP+OSD, and Relay-BP for qLDPC codes, alongside NVIDIA Ising AI pre-decoders for surface and color codes. Although these tools are presently demonstrated most directly for different code families, they point toward a broader path for structure-aware, GPU- and AI-accelerated qLDPC decoding and real-time QEC infrastructure.