Welcome to the Scalable Quantum Error Correction Workshop
Organized as part of IEEE Quantum Week (QCE 2025)
Date: Tuesday, September 2, 2025
Location: Albuquerque Convention Center

Workshop Theme and Objectives
The goal of this workshop is to explore scalable quantum error correction techniques for fault-tolerant quantum computing. The event will feature invited talks from researchers and industry leaders at the forefront of this field, as well as a concluding panel discussion focused on identifying key open problems—both foundational and practical—in scaling QEC systems. We will also explore recent results and advances that bring us closer to building scalable and implementable quantum error correction.
Workshop date
- Tuesday, September 2, 2025 (10 am - 5 pm)
Schedule
Time | Program |
---|---|
10:00 – 10:30 | Eddie Schoute (IBM) – Tour de gross: A modular quantum computer based on bivariate bicycle codes |
10:30 – 11:00 | Dolev Bluvstein (Harvard) – Architectural mechanisms of a universal fault-tolerant quantum computer |
11:00 – 11:30 | Zhiyang (Sunny) He (MIT) – Extractors: QLDPC Architectures for Efficient Pauli-Based Computation |
11:30 – 13:00 | Lunch Break |
13:00 – 13:30 | Christopher Pattison (Caltech) – Hierarchical memories: Simulating quantum LDPC codes with local gates |
13:30 – 14:00 | Madelyn Cain (Harvard) – Fast correlated decoding of transversal logical algorithms |
14:00 – 14:30 | Namitha Liyanage (Yale/Riverlane) – From Vertex-Level to Network-Level Parallelism: Scaling QEC Decoding |
14:30 – 15:00 | Break |
15:00 – 15:30 | John Robinson (QuEra) – Experimental demonstration of logical magic state distillation |
15:30 – 16:30 | Panel Discussion: Pathways to Scalable QEC – with invited speakers as esteemed panelists |
16:30 – 17:00 | Open Q&A and Networking |
Invited Speakers
- Eddie Schoute (IBM)
- Dolev Bluvstein (Harvard)
- Zhiyang (Sunny) He (MIT)
- Chris Pattison (Caltech)
- Namitha Liyanage (Yale/Riverlane)
- Madelyn Cain (Harvard/Google)
- John Robinson (QuEra)
Topics Covered
- Quantum error correction codes
- Efficient decoding algorithms and implementations
- FTQC architectures for large-scale systems
- Logical operations and error rates at scale
- Design tradeoffs: overhead vs. performance
- Interplay between physical hardware constraints and QEC
Organizers / Program Chairs
- Madelyn Cain
- Nithin Raveendran
- Valentin Savin
- Bane Vasić
- Qian Xu
Contact
Questions? Please contact nithin@arizona.edu
Webpage last updated: Aug 26, 2025